As a verification eng., you will work with IP architect to understand IP features, create testbench architecture plan, work with IP designers to develop testplan, perform detailed testing of IP features and ensure coverage is met.
You will need to ensure the IP is compatible with industry standard synthesis & simulator tools. You will also co-ordinate with IP designer on IP release mechanism for testing.
You are also expected to develop scripts in Python and other script language to automate the soft IP development and testing process.
Bachelors of Engineering or better in Computer Engineering or related field.
Experienced in using one or more of industry standard simulators & synthesis tools
Hands-on experience with SystemVerilog / UVM
5 years : design verification
Licenses & Certifications