Develop characterization test plans using established methodologies targeted on chip IP functions and features.
Execute characterization of target chip IP features using wafer-level ATE, package-level ATE, and package-level bench platforms across process, temperature, and voltage conditions.
Apply statistical analysis on collected characterization data to define key product datasheet parameters and report out results.
Identify and analyze to root cause product marginalities, communicating and coordinating root cause closure to appropriate cross-functional team (eg.
Applications Engineering, Design Engineering, etc.)
Design and implement test circuits using FPGA fabric and embedded IP.
Develop bench automation and data collection scripts and programs.
Design and develop ATE and bench HW.
Drive all product issues to resolution.
Plan and execute testing of samples (ie. AS, ES), ensuring timely delivery of tested samples to internal and external customers.
Analyze and report out on test yield and test time.
2-3+ years individual contributor in Product or Test Engineering
BS degree (ECE, CoE, EE, Physics)
Good working knowledge of semiconductor devices and test methodologies
Experience in ATE test program development and integration an advantage, Nextest Magnum 1 or Magnum 2 preferred
Experience in hardware development (loadboard, probecard, bench board) an advantage
Experience in IC characterization and / or failure analysis using various bench tools (i.e. Oscilloscope, Pattern Generators, Data Timing Generator, Multimeters, etc)
Experience with WAT / etest, wafer sort, package assembly, final test (i.e. full backend IC process)
Experience in Programmable Logic is an advantage
Experience in RTL Design, Design Verification an advantage
Knowledge in test, DFT methodologies (ie. scan, BIST), and fault grade methodologies an advantage
Knowledge in Hardware Description Language such as Verilog or VHDL an advantage
Knowledge in programming languages (ie. Python, C++)
Knowledge of Statistical Process Control an advantage
Experience in the use statistical analysis SW (ie. SAS JMP, R) an advantage.
Knowledge in Yield Analysis an advantage
Excellent verbal and written English skills. Demonstrated ability to work with multiple groups and across cultures
Good analytical and problem solving abilities
Strong Windows, Unix, and MS Office skills
Curious with strong self-motivation to learn and explore
Bachelors of Engineering or better in Electronics and Communication Engineering or related field.
RTL Design, Design Verification
WAT / etest, wafer sort, package assembly, final test (i.e. full backend IC process)
IC characterization and / or failure analysis using various bench tools (i.e. Oscilloscope, Pattern Generators, Data Timing Generator, Multimeters, etc)
hardware development (loadboard, probecard, bench board)
ATE test program development and integration an advantage, Nextest Magnum 1 or Magnum 2
2-3 years : Product or Test Engineering
Licenses & Certifications