Develop comprehensive verification plans, clear metrics and continuously measure progress against the plan throughout the project
Verify design blocks, sub systems and full chip using assertion-based verification, formal verification, directed tests and randomized tests
Understand the specifications, use cases and develop System Verilog and C’ based testbenches in UVM environment
Design and develop testbench components such as Universal Verification Components, BFMs and verification tools
Define and design verification regression environment
Perform Functional coverage, RTL code coverage, assertion coverage, and gate level simulations
Collaborate with design engineers, IP developers and SW developers to deliver high quality SoC verification on aggressive time schedules
Develop best practices and world class methods for SoC verification
Highly skilled in debugging and analyzing complex digital designs.
Expert HDL and HVL Languages and methodologies (Verilog, VHDL, SystemVerilog, UVM / OVM etc.)
Familiar with ASIC / FPGA / SoC verification process / development cycle.
Expert in using simulation tools like Cadence IES / Xcelium, Synopsys VCS or Mentor’s Questa
Have hands-on experience in Python, Perl or shell scripting, TCL, make.
Strong communication, analytical and documentation skills and ability to interface with other groups / site.
Stay up to date on industry trends and direction of verification technology development
Bachelors or better in Electronics Engineering or related field.
HDL and HVL Languages and methodologies (Verilog, VHDL, SystemVerilog, UVM / OVM etc.)
debugging and analyzing complex digital designs
Licenses & Certifications