Soft IP Verification Egineer
Lattice Semiconductor
Filinvest Alabang, PHL
6d ago


As a verification eng., you will work with IP architect to understand IP features, create testbench architecture plan, work with IP designers to develop testplan, perform detailed testing of IP features and ensure coverage is met.

You will need to ensure the IP is compatible with industry standard synthesis & simulator tools. You will also co-ordinate with IP designer on IP release mechanism for testing.

You are also expected to develop scripts in Python and other script language to automate the soft IP development and testing process.

Requirements :

  • BS or MS in Computer / Electronics / Electrical Engineering with 5 years of relevant design verification experience
  • Hands-on experience with SystemVerilog / UVM
  • Experienced in using one or more of industry standard simulators & synthesis tools
  • Familiarity with source code system (Perforce) , Jenkins etc. added advantage
  • Good understanding of FPGA implementation flow from Synthesis to bit-stream generation
  • Excellent debugging skills to identify & fix bugs
  • Deep understanding of DDR, PCIe, Ethernet, AMBA, and serial communication protocols desired
  • Excellent communication skills to coordinate IP development work with remote teams
  • Good to have skills : C / C++, Python
  • Required

    Bachelors of Engineering or better in Electronics Engineering or related field.


    5 years : design verification experience

    SystemVerilog / UVM

    Licenses & Certifications

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